An external controller that is associated with a memory device may employ a DQS-DQ delay in connection with write operations directed to the memory device. A DQ signal in accordance with the present disclosure is a signal that carries data written from an external controller to a memory device. The DQS signal is a data strobe signal that provides an indication from the external controller to the memory that data is available on the DQ signal lines for capture by the memory. The DQS signal may be received at a memory through a memory pad, pass through an internal signal pathway, and arrive at one or more data latches where the DQS signal clocks the incoming write data carried by the DQ signal. The DQ signal generally lags behind the DQS signal by a certain delay so as to allow the DQS signal to propagate through the internal DQS signal pathway. The amount by which the external controller delays the DQ signal may be set through a DQS training procedure that measures a loop delay associated with the internal DQS signal pathway.
The loop delay of an internal DQS signal pathway may vary under different operating conditions. For example, variations in temperature may cause changes in the rate at which the DQS signal propagates through the various gates or other stages associated with the internal DQS signal pathway. Variations in the power supply voltage of the memory device may also cause changes in the rate that the DQS signal propagates through the internal DQS signal pathway. Process variations may also be a contributing factor to delay variations. The various factors that may affect propagation times in the internal DQS signal pathway are generally referred to herein as PVT variations. Changes in the loop delay of the internal DQS signal pathway that result from PVT variations may result in the DQS-DQ delay of the external controller becoming inaccurate.
Memory devices typically address the issue of a changing loop delay by continually monitoring the loop delay and adjusting the DQS-DQ delay accordingly. In order to track changes in the loop delay, the controller may execute multiple DQS training procedures during the operation of the memory. These extra controller operations can become costly in terms of speed, efficiency, and power consumption. Accordingly, there is a need in the art for a memory to have a DQ-DS delay that is less variable such that an external controller may minimize or eliminate multiple DQS training procedures.